The present invention provides certain improvements in microelectronic component testing. More particularly, certain embodiments of the invention provide methods and systems for verifying planarity of elements of a microelectronic component test system, e.g., a semiconductor wafer prober.
The microelectronics industry is highly competitive and most microelectronics manufacturers are highly sensitive to quality and cost considerations. Most microelectronics manufacturers require that suppliers of microelectronic components test the performance of each microelectronic component before shipment to minimize the manufacturer's product losses. Microelectronics are commonly tested by establishing temporary electrical connections between a test system and electrical terminals on the microelectronic component.
Temporary electrical connection between the test system and the terminals of the microelectronic component is conventionally established using a test card carrying a plurality of test probes. In some circumstances, the probes comprise cantilevered wire probes which are coupled to an epoxy ring or the like. The tips of the wire probes are rearranged relative to one another to position their ends in an array that matches an array of the terminals on the microelectronic component. In another conventional system, the probes of the test card may comprise pins, typically either a length of wire or a spring-biased mechanism, e.g., POGO PINS, commercially available from Pogo Industries of Kansas City, Kans., USA. Again, the ends of these pins will be arranged in an array intended to match the array of terminals on the microelectronic component.
As microelectronic components and the terminals carried by those components are made progressively smaller, it becomes increasingly difficult to insure proper contact between the probes of the test card and the terminals of the microelectronic component. Sometimes when these elements are not precisely aligned, one or more of the probes will not establish adequate contact with the intended terminal on the microelectronic component. When this data is analyzed, the test system may improperly indicate that an acceptable microelectronic component is defective. Such false rejections can be expensive and time consuming.
One factor which can affect proper alignment of the test probes with the terminals on the microelectronic component can be the relative planarity of the test card and the terminal-bearing surface of the microelectronic component. The probe tips are often intended to lie generally in a single plane. If this probe tip plane and a plane of the microelectronic component terminals are not parallel to one another, probe tips intended to contact terminals on one side of the array may be overly compressed or stressed, while terminals on the other side of the terminal array do not adequately contact the intended probes. If the microelectronic component is pushed harder against the probes, these variations in relative planarity can be overcome. Unfortunately, this can place undue stress on the microelectronic component being tested and on the test card.